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| Preliminary Technical Data FEATURES 2 pF off capacitance 1 pC charge injection 33 V supply range 120 on resistance Fully specified at +12 V, 15 V No VL supply required 3 V logic-compatible inputs Rail-to-rail operation 16-lead TSSOP and 12-lead LFCSP packages Typical power consumption: <0.03 W 2 pF Off Capacitance, 1 pC Charge Injection, 15 V/12 V iCMOSTM Dual SPDT Switch ADG1236 FUNCTIONAL BLOCK DIAGRAM ADG1236 S1A D1 S1B IN1 IN2 S2A D2 04776-0-001 S2B APPLICATIONS Automatic test equipment Data aquisition systems Battery-powered systems Sample-and-hold systems Audio signal routing Communication systems SWITCHES SHOWN FOR A LOGIC 1 INPUT Figure 1. GENERAL DESCRIPTION The ADG1236 is a monolithic CMOS device containing two independently selectable SPDT switches. It is designed on an iCMOS process. iCMOS (industrial-CMOS) is a modular manufacturing process combining high voltage CMOS (complementary metal-oxide semiconductor) and bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 30 V operation in a footprint that no previous generation of high voltage parts has been able to achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can tolerate high supply voltages, while providing increased performance, dramatically lower power consumption, and reduced package size. The ultralow capacitance and charge injection of the part make it an ideal solution for data acquisition and sample-and-hold applications, where low glitch and fast settling are required. Fast switching speed coupled with high signal bandwidth make the part suitable for video signal switching. iCMOS construction ensures ultralow power dissipation, making the part ideally suited for portable and battery-powered instruments. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. Both switches exhibit break-before-make switching action for use in multiplexer applications. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. 6. 2 pF off capacitance (15 V supply). 1 pC charge injection. 3 V logic-compatible digital inputs: VIH = 2.0 V, VIL = 0.8 V. No VL logic power supply required. Ultralow power dissipation: <0.03 W. 16-lead TSSOP and 12-lead 3 mm x 3 mm LFCSP packages. Rev. PrD Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved. ADG1236 TABLE OF CONTENTS Specifications..................................................................................... 3 Dual Supply ................................................................................... 3 Single Supply ................................................................................. 4 Absolute Maximum Ratings............................................................ 6 Truth Table For Switches ............................................................. 6 ESD Caution.................................................................................. 6 Preliminary Technical Data Pin Configurations and Function Descriptions ............................7 Terminology .......................................................................................8 Typical Performance Characteristics ..............................................9 Test Circuits..................................................................................... 12 Outline Dimensions ....................................................................... 14 Ordering Guide .......................................................................... 14 REVISION HISTORY 11/04--Revision PrD: Preliminary Version Rev. PrD | Page 2 of 16 Preliminary Technical Data SPECIFICATIONS DUAL SUPPLY VDD = 15 V 10%, VSS = -15 V 10%, GND = 0 V, unless otherwise noted. Table 1. Parameters ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match between Channels (RON) On Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off) Drain Off Leakage, ID (Off) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS2 tON tOFF Break-before-Make Time Delay, tD Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise -3 dB Bandwidth CS (Off) CD(Off) CD, CS (On) POWER REQUIREMENTS IDD IDD ISS 25C 85C Y Version1 VDD to VSS 120 5 220 260 Unit V typ max typ max typ max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ % typ MHz typ pF typ pF typ pF typ A typ A max A typ A max A typ A max ADG1236 Test Conditions/Comments VS = 10 V, IS = -10 mA; Figure 21 VS = 10 V, IS = -10 mA 25 50 0.01 0.5 0.01 0.5 0.04 1 VS = -5 V/0 V/+5 V; IS = -10 mA VDD = +10 V, VSS = -10 V VS = 0 V/10 V, VD = 10 V/0 V; Figure 22 VS = 0 V/10 V, VD = 10 V/0 V; Figure 22 VS = VD = 0 V or 10 V; Figure 23 1 1 2 5 5 5 2.0 0.8 0.005 0.5 5 50 20 15 1 75 85 0.002 700 2 2 5 0.001 5.0 150 300 0.001 5.0 100 40 1 VIN = VINL or VINH RL = 50 , CL = 35 pF VS = 10 V; Figure 24 RL = 50 , CL = 35 pF VS = 10 V; Figure 24 RL = 50 , CL = 35 pF VS1 = VS2 = 10 V; Figure 25 VS = 0 V, RS = 0 , CL = 1 nF; Figure 26 RL = 50 , CL = 5 pF, f = 1 MHz; Figure 27 RL = 50 , CL = 5 pF, f = 1 MHz; Figure 28 RL = 600 , 5 V rms, f = 20 Hz to 20 kHz RL = 50 , CL = 5 pF; Figure 29 VDD = +16.5 V, VSS = -16.5 V Digital Inputs = 0 V or VDD Digital Input = 5 V Digital Inputs = 0 V or VDD Rev. PrD | Page 3 of 16 ADG1236 Parameters IGND IGND 25C 0.001 150 300 85C Y Version1 5.0 Unit A typ A max A typ A max Preliminary Technical Data Test Conditions/Comments Digital Inputs = 0 V or VDD Digital Input = 5 V 1 2 Temperature range for Y Version is -40C to +125C. Guaranteed by design, not subject to production test. SINGLE SUPPLY VDD = 12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 2. Parameters ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match between Channels (RON) On Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off) Drain Off Leakage, ID (Off) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS2 tON tOFF Break-before-Make Time Delay, tD Charge Injection Off Isolation Channel-to-Channel Crosstalk -3 dB Bandwidth CS (Off) CD (Off) CD, CS (On) 25C 85C Y Version1 0 V to VDD 220 10 Unit V typ max typ max typ nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns max ns typ ns min pC typ pC typ dB typ dB typ MHz typ pF typ pF typ pF typ Test Conditions/Comments VS = +10 V, IS = -10 mA; Figure 21 VS = +10 V, IS = -10 mA 40 0.01 0.5 0.01 0.5 0.04 1 VS = +3 V/+6 V/+9 V, IS = -10 mA VDD = 12 V VS = 1 V/10 V, VD = 10 V/1 V; Figure 22 VS = 1 V/10 V, VD = 10 V/1 V; Figure 22 VS = VD = 1 V or 10 V, Figure 23 1 1 2 2.0 0.8 5 5 5 0.001 0.5 5 50 15 15 1 5 75 85 700 2 2 5 VIN = VINL or VINH RL = 50 , CL = 35 pF VS = 8 V; Figure 24 RL = 50 , CL = 35 pF VS = 8 V; Figure 24 RL = 50 , CL = 35 pF VS1 = VS2 = 8 V; Figure 25 VS = 0 V, RS = 0 , CL = 1 nF; Figure 26 RL = 50 , CL = 5 pF, f = 1 MHz; Figure 27; RL = 50 , CL = 5 pF, f = 1 MHz; Figure 28 RL = 50 , CL = 5 pF; Figure 29 Rev. PrD | Page 4 of 16 Preliminary Technical Data Parameters POWER REQUIREMENTS IDD IDD 25C 0.001 5.0 150 300 85C Y Version1 Unit A typ A max A typ A max ADG1236 Test Conditions/Comments VDD = 13.2 V Digital Inputs = 0 V or VDD Digital Inputs = 5 V 1 2 Temperature range for Y Version is -40C to +125C. Guaranteed by design, not subject to production test. Rev. PrD | Page 5 of 16 ADG1236 ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. Table 3. Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs1 Digital Inputs1 Peak Current, S or D Continuous Current, S or D Operating Temperature Range Industrial (B Version) Automotive (Y Version) Storage Temperature Range Junction Temperature 16-Lead TSSOP, JA Thermal Impedance 12-Lead LFCSP, JA Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 s) Infrared (15 s) Ratings 38 V -0.3 V to +25 V +0.3 V to -25 V VSS - 0.3 V to VDD + 0.3 V GND - 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first 100 mA (pulsed at 1 ms, 10% duty cycle max) 30 mA -40C to +85C -40C to +125C -65C to +150C 150C 150.4C/W TBDC/W Preliminary Technical Data Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition s above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. TRUTH TABLE FOR SWITCHES Table 4. IN 0 1 Switch A Off On Switch B On Off 215C 220C 1 Over voltages at IN, S, or D are clamped by internal diodes. Current should be limited to the maximum ratings given. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. PrD | Page 6 of 16 Preliminary Technical Data PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 12 S1A 11 IN1 IN1 1 S1A 2 D1 3 S1B 4 16 NC 15 NC 14 NC ADG1236 13 VDD TOP VIEW VSS 5 (Not to Scale) 12 S2B 11 D2 10 S2A 04776-0-002 ADG1236 D1 1 S1B 2 VSS 3 PIN 1 INDICATOR 10 NC 9 VDD 8 S2B 7 D2 04776-0-003 ADG1236 TOP VIEW (Not to Scale) GND 6 NC 7 NC 8 NC = NO CONNECT Figure 2.TSSOP Pin Configuration Figure 3. LFCSP Pin Configuration Table 5. Pin Function Descriptions Pin No. TSSOP LFCSP 1 11 2 12 3 1 4 2 5 3 6 4 7, 8, 14-16 10 9 5 10 6 11 7 12 8 13 9 Mnemonic IN1 S1A D1 S1B VSS GND NC IN2 S2A D2 S2B VDD Function Logic Control Input. Source Terminal. Can be an input or output. Drain Terminal. Can be an input or output. Source Terminal. Can be an input or output. Most Negative Power Supply Potential. Ground (0 V) Reference. No Connect. Logic Control Input. Source Terminal. Can be an input or output. Drain Terminal. Can be an input or output. Source Terminal. Can be an input or output. Most Positive Power Supply Potential. Rev. PrD | Page 7 of 16 GND 4 S2A 6 IN2 5 9 IN2 NC = NO CONNECT ADG1236 TERMINOLOGY IDD The positive supply current. ISS The negative supply current. VD (VS) The analog voltage on Terminals D and S. RON The ohmic resistance between D and S. RFLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on resistance, as measured over the specified analog signal range. IS (Off) The source leakage current with the switch off. ID (Off) The drain leakage current with the switch off. ID, IS (On) The channel leakage current with the switch on. VINL The maximum input voltage for Logic 0. VINH The minimum input voltage for Logic 1. IINL (IINH) The input current of the digital input. CS (Off) The off switch source capacitance, measured with reference to ground. Preliminary Technical Data CD (Off) The off switch drain capacitance, measured with reference to ground. CD, CS (On) The on switch capacitance, measured with reference to ground. CIN The digital input capacitance. tON The delay between applying the digital control input and the output switching on. See Figure 24. tOFF The delay between applying the digital control input and the output switching off. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Off Isolation A measure of unwanted signal coupling through an off switch. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. Bandwidth The frequency at which the output is attenuated by 3 dB. On Response The frequency response of the on switch. Insertion Loss The loss due to the on resistance of the switch. Rev. PrD | Page 8 of 16 Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS ADG1236 Figure 4. On Resistance as a Function of VD (VS) for Single Supply Figure 7. On Resistance as a Function of VD (VS) for Different Temperatures, Single Supply Figure 5, On Resistance as a Function of VD (VS) for Dual Supply Figure 8, On Resistance as a Function of VD (VS) for Different Temperatures, Dual Supply Figure 6. On Resistance as a Function of VD (VS) for Different Temperatures, Single Supply Figure 9. Leakage Current as a Function of VD (VS) Rev. PrD | Page 9 of 16 ADG1236 Preliminary Technical Data Figure 10. Leakage Currents as a Function of VD (VS) Figure 13. Leakage Currents as a Function of Temperature Figure 11. Leakage Current as a Function of VD (VS) Figure 14. Supply Currents vs. Input Switching Frequency Figure 12. Leakage Currents as a Function of Temperature Figure 15. Charge Injection vs. Source Voltage Rev. PrD | Page 10 of 16 Preliminary Technical Data ADG1236 Figure 16. tON/tOFF Times vs. Temperature Figure 19. On Response vs. Frequency Figure 17. Off Isolation vs. Frequency Figure 20. THD + N vs. Frequency Figure 18. Crosstalk vs. Frequency Rev. PrD | Page 11 of 16 ADG1236 TEST CIRCUITS V Preliminary Technical Data IS (OFF) S D 04776-0-020 ID (OFF) S D A 04776-0-021 ID (ON) NC A IDS S D A VD 04776-0-022 VS VS VD NC = NO CONNECT Figure 21. Test Circuit 1--On Resistance Figure 22. Test Circuit 2-- Off Resistance Figure 23. Test Circuit 3--On Leakage 0.1F VDD VSS 0.1F VIN 50% 50% VDD VS SB SA IN VIN GND VSS D RL 50 CL 35pF VOUT VIN 50% 90% 50% 90% VOUT tON tOFF Figure 24. Test Circuit 4--Switching Times 0.1F VDD VSS 0.1F VIN VDD VS SB SA IN VIN GND VSS D RL 50 CL 35pF VOUT VOUT 80% tBBM 04776-0-023 tBBM 04776-0-024 Figure 25. Test Circuit 5--Break-before-Make Time Delay 0.1F VDD VSS 0.1F VIN (NORMALLY CLOSED SWITCH) ON NC VOUT CL 1nF VIN (NORMALLY OPEN SWITCH) VOUT VOUT OFF VDD D VSS SB VS SA IN VIN GND Figure 26. Test Circuit 6--Charge Injection Rev. PrD | Page 12 of 16 04776-0-025 QINJ = CL x VOUT Preliminary Technical Data VDD VDD 0.1F VSS 0.1F NETWORK ANALYZER NC IN SA D ADG1236 VSS 0.1F 0.1F VDD VSS NETWORK ANALYZER VOUT RL 50 VDD SA VSS 50 SB 50 VS VOUT 04776-0-026 SB IN VS GND D R 50 VIN GND RL 50 OFF ISOLATION = 20 LOG VOUT VS CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG VOUT VS Figure 27. Test Circuit 7--Off Isolation Figure 29. Test Circuit 9-- Bandwidth VDD 0.1F VSS 0.1F NETWORK ANALYZER NC 50 VDD 0.1F VSS 0.1F AUDIO PRECISION VDD VSS IN SA D SB 50 VS VDD S RL 50 VOUT VSS RS VIN GND IN D VIN 04776-0-027 VS V p-p RL 600 VOUT 04776-0-029 INSERTION LOSS = 20 LOG VOUT WITH SWITCH VOUT WITHOUT SWITCH GND Figure 28. Test Circuit 8--Channel-to-Channel Crosstalk Figure 30. Test Circuit 10--THD + Noise Rev. PrD | Page 13 of 16 04776-0-028 ADG1236 OUTLINE DIMENSIONS 5.10 5.00 4.90 Preliminary Technical Data 16 9 4.50 4.40 4.30 1 8 6.40 BSC PIN 1 1.20 MAX 0.20 0.09 0.65 BSC 0.30 0.19 COPLANARITY 0.10 SEATING PLANE 8 0 0.75 0.60 0.45 0.15 0.05 COMPLIANT TO JEDEC STANDARDS MO-153AB Figure 31. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in inches and (millimeters 3.00 BSC SQ 0.60 MAX 0.75 0.55 0.35 PIN 1 INDICATOR *1.45 1.30 SQ 1.15 0.45 PIN 1 INDICATOR TOP VIEW 2.75 BSC SQ EXPOSED PAD (BOTTOM VIEW) 12 MAX 1.00 0.85 0.80 SEATING PLANE 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF 9 8 7 10 11 12 1 2 3 6 5 4 0.25 MIN 0.50 BSC COPLANARITY 0.08 *COMPLIANT TO JEDEC STANDARDS MO-220-VEED-1 EXCEPT FOR EXPOSED PAD DIMENSION. Figure 32. 12-Lead Lead Frame Chip Scale Package [VQ_LFCSP] 3 mm x 3 mm Body, Very Thin Quad (CP-12-1) Dimensions shown in millimeters ORDERING GUIDE Model ADG1236YRU ADG1236YCP Temperature Range -40C to +125C -40C to +125C Package Description Thin Shrink Small Outline Package (TSSOP) Lead Frame Chip Scale Package (LFCSP) Package Option RU-16 CP-12-1 Rev. PrD | Page 14 of 16 Preliminary Technical Data NOTES ADG1236 Rev. PrD | Page 15 of 16 ADG1236 NOTES Preliminary Technical Data (c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR04776-0-11/04(PrD) Rev. PrD | Page 16 of 16 |
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